Searched refs:mmVM_L2_CNTL2 (Results 1 – 16 of 16) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfxhub_v1_0.c | 190 tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2); in gfxhub_v1_0_init_cache_regs()
193 WREG32_SOC15_RLC(GC, 0, mmVM_L2_CNTL2, tmp); in gfxhub_v1_0_init_cache_regs()
|
| H A D | mmhub_v1_0.c | 176 tmp = RREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2); in mmhub_v1_0_init_cache_regs()
179 WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp); in mmhub_v1_0_init_cache_regs()
|
| H A D | gmc_v6_0.c | 487 WREG32(mmVM_L2_CNTL2, in gmc_v6_0_gart_enable()
592 WREG32(mmVM_L2_CNTL2, 0); in gmc_v6_0_gart_disable()
|
| H A D | gmc_v8_0.c | 845 tmp = RREG32(mmVM_L2_CNTL2); in gmc_v8_0_gart_enable()
848 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v8_0_gart_enable()
974 WREG32(mmVM_L2_CNTL2, 0); in gmc_v8_0_gart_disable()
|
| H A D | gmc_v7_0.c | 632 WREG32(mmVM_L2_CNTL2, tmp); in gmc_v7_0_gart_enable()
742 WREG32(mmVM_L2_CNTL2, 0); in gmc_v7_0_gart_disable()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
| H A D | gmc_7_0_d.h | 542 #define mmVM_L2_CNTL2 0x501 macro
|
| H A D | gmc_8_2_d.h | 600 #define mmVM_L2_CNTL2 0x501 macro
|
| H A D | gmc_6_0_d.h | 1258 #define mmVM_L2_CNTL2 0x0501 macro
|
| H A D | gmc_7_1_d.h | 575 #define mmVM_L2_CNTL2 0x501 macro
|
| H A D | gmc_8_1_d.h | 598 #define mmVM_L2_CNTL2 0x501 macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/ |
| H A D | mmhub_9_3_0_offset.h | 1282 #define mmVM_L2_CNTL2 … macro
|
| H A D | mmhub_9_1_offset.h | 1298 #define mmVM_L2_CNTL2 … macro
|
| H A D | mmhub_1_0_offset.h | 1266 #define mmVM_L2_CNTL2 … macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_0_offset.h | 1167 #define mmVM_L2_CNTL2 … macro
|
| H A D | gc_9_1_offset.h | 1193 #define mmVM_L2_CNTL2 … macro
|
| H A D | gc_9_2_1_offset.h | 1131 #define mmVM_L2_CNTL2 … macro
|