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Searched refs:mmVM_CONTEXT0_CNTL (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_0.c222 tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_enable_system_domain()
230 WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp); in gfxhub_v1_0_enable_system_domain()
349 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, in gfxhub_v1_0_gart_disable()
432 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL); in gfxhub_v1_0_init()
438 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in gfxhub_v1_0_init()
H A Dgmc_v6_0.c515 WREG32(mmVM_CONTEXT0_CNTL, in gmc_v6_0_gart_enable()
592 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v6_0_gart_disable()
1047 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1049 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
1055 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v6_0_vm_fault_interrupt_state()
1057 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v6_0_vm_fault_interrupt_state()
H A Dgmc_v7_0.c658 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_gart_enable()
662 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_gart_enable()
741 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v7_0_gart_disable()
1238 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1240 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
1248 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v7_0_vm_fault_interrupt_state()
1250 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v7_0_vm_fault_interrupt_state()
H A Dmmhub_v1_0.c203 tmp = RREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_enable_system_domain()
208 WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_CNTL, tmp); in mmhub_v1_0_enable_system_domain()
398 WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL, in mmhub_v1_0_gart_disable()
484 SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL); in mmhub_v1_0_init()
490 hub->ctx_distance = mmVM_CONTEXT1_CNTL - mmVM_CONTEXT0_CNTL; in mmhub_v1_0_init()
H A Dgmc_v8_0.c889 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_gart_enable()
893 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_gart_enable()
973 WREG32(mmVM_CONTEXT0_CNTL, 0); in gmc_v8_0_gart_disable()
1400 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1402 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
1410 tmp = RREG32(mmVM_CONTEXT0_CNTL); in gmc_v8_0_vm_fault_interrupt_state()
1412 WREG32(mmVM_CONTEXT0_CNTL, tmp); in gmc_v8_0_vm_fault_interrupt_state()
H A Dsi.c91 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8,
/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h545 #define mmVM_CONTEXT0_CNTL 0x504 macro
H A Dgmc_8_2_d.h603 #define mmVM_CONTEXT0_CNTL 0x504 macro
H A Dgmc_6_0_d.h1217 #define mmVM_CONTEXT0_CNTL 0x0504 macro
H A Dgmc_7_1_d.h578 #define mmVM_CONTEXT0_CNTL 0x504 macro
H A Dgmc_8_1_d.h601 #define mmVM_CONTEXT0_CNTL 0x504 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_3_0_offset.h1340 #define mmVM_CONTEXT0_CNTL macro
H A Dmmhub_9_1_offset.h1356 #define mmVM_CONTEXT0_CNTL macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1232 #define mmVM_CONTEXT0_CNTL macro
H A Dgc_9_1_offset.h1251 #define mmVM_CONTEXT0_CNTL macro
H A Dgc_9_2_1_offset.h1189 #define mmVM_CONTEXT0_CNTL macro