Searched refs:mmVGT_ESGS_RING_SIZE_Sienna_Cichlid (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v10_0.c | 85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1 macro
7188 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid); in gfx_v10_0_check_grbm_cam_remapping()
7189 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0); in gfx_v10_0_check_grbm_cam_remapping()
7192 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) { in gfx_v10_0_check_grbm_cam_remapping()
7196 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data); in gfx_v10_0_check_grbm_cam_remapping()
7276 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) << in gfx_v10_0_setup_grbm_cam_remapping()
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