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Searched refs:mmVGA_HDP_CONTROL (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v6_0.c246 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v6_0_mc_program()
248 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v6_0_mc_program()
H A Dgmc_v7_0.c283 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v7_0_mc_program()
285 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v7_0_mc_program()
H A Dgmc_v8_0.c458 tmp = RREG32(mmVGA_HDP_CONTROL); in gmc_v8_0_mc_program()
460 WREG32(mmVGA_HDP_CONTROL, tmp); in gmc_v8_0_mc_program()
H A Ddce_v8_0.c400 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v8_0_set_vga_render_state()
405 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v8_0_set_vga_render_state()
H A Ddce_v10_0.c449 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v10_0_set_vga_render_state()
454 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
H A Ddce_v11_0.c471 tmp = RREG32(mmVGA_HDP_CONTROL); in dce_v11_0_set_vga_render_state()
476 WREG32(mmVGA_HDP_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4383 #define mmVGA_HDP_CONTROL 0x00CA macro
H A Ddce_8_0_d.h5142 #define mmVGA_HDP_CONTROL 0xca macro
H A Ddce_10_0_d.h6025 #define mmVGA_HDP_CONTROL 0xca macro
H A Ddce_11_0_d.h6102 #define mmVGA_HDP_CONTROL 0xca macro
H A Ddce_11_2_d.h7776 #define mmVGA_HDP_CONTROL 0xca macro
H A Ddce_12_0_offset.h570 #define mmVGA_HDP_CONTROL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h33 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_3_0_1_offset.h164 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_1_0_offset.h404 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_2_1_0_offset.h108 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_3_0_2_offset.h48 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_2_0_0_offset.h48 #define mmVGA_HDP_CONTROL … macro
H A Ddcn_3_0_0_offset.h30 #define mmVGA_HDP_CONTROL … macro