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Searched refs:mmVCE_VCPU_CACHE_SIZE0 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h59 #define mmVCE_VCPU_CACHE_SIZE0 0x800A macro
H A Dvce_2_0_d.h30 #define mmVCE_VCPU_CACHE_SIZE0 0x800a macro
H A Dvce_3_0_d.h30 #define mmVCE_VCPU_CACHE_SIZE0 0x800a macro
H A Dvce_4_0_offset.h34 #define mmVCE_VCPU_CACHE_SIZE0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c285 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); in vce_v4_0_sriov_start()
665 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_SIZE0), size); in vce_v4_0_mc_resume()
H A Dvce_v3_0.c574 WREG32(mmVCE_VCPU_CACHE_SIZE0, size); in vce_v3_0_mc_resume()