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Searched refs:mmVCE_RB_WPTR2 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_2_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
H A Dvce_3_0_d.h40 #define mmVCE_RB_WPTR2 0x805f macro
H A Dvce_4_0_offset.h78 #define mmVCE_RB_WPTR2 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c84 return RREG32(mmVCE_RB_WPTR2); in vce_v2_0_ring_get_wptr()
101 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
257 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
H A Dvce_v1_0.c97 return RREG32(mmVCE_RB_WPTR2); in vce_v1_0_ring_get_wptr()
114 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v1_0_ring_set_wptr()
407 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v1_0_start()
H A Dvce_v3_0.c124 v = RREG32(mmVCE_RB_WPTR2); in vce_v3_0_ring_get_wptr()
155 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
289 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()