Home
last modified time | relevance | path

Searched refs:mmUVD_VCPU_NONCACHE_OFFSET0 (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h721 #define mmUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_2_0_0_offset.h650 #define mmUVD_VCPU_NONCACHE_OFFSET0 … macro
H A Dvcn_3_0_0_offset.h1097 #define mmUVD_VCPU_NONCACHE_OFFSET0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c424 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_0_mc_resume()
517 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
H A Dvcn_v2_5.c511 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
603 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
H A Dvcn_v3_0.c538 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v3_0_mc_resume()
629 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()