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Searched refs:mmUVD_VCPU_INT_EN (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h523 #define mmUVD_VCPU_INT_EN … macro
H A Dvcn_2_0_0_offset.h546 #define mmUVD_VCPU_INT_EN … macro
H A Dvcn_3_0_0_offset.h839 #define mmUVD_VCPU_INT_EN … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_5.c858 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), in vcn_v2_6_enable_ras()