| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 91 #define mmUVD_VCPU_CACHE_SIZE0 0x3D37 macro
|
| H A D | uvd_4_2_d.h | 61 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
|
| H A D | uvd_3_1_d.h | 63 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
|
| H A D | uvd_5_0_d.h | 67 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
|
| H A D | uvd_6_0_d.h | 83 #define mmUVD_VCPU_CACHE_SIZE0 0x3d83 macro
|
| H A D | uvd_7_0_offset.h | 180 #define mmUVD_VCPU_CACHE_SIZE0 … macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 366 #define mmUVD_VCPU_CACHE_SIZE0 … macro
|
| H A D | vcn_2_5_offset.h | 687 #define mmUVD_VCPU_CACHE_SIZE0 … macro
|
| H A D | vcn_2_0_0_offset.h | 616 #define mmUVD_VCPU_CACHE_SIZE0 … macro
|
| H A D | vcn_3_0_0_offset.h | 1063 #define mmUVD_VCPU_CACHE_SIZE0 … macro
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v2_0.c | 399 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_0_mc_resume()
469 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
472 UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1956 SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_0_start_sriov()
|
| H A D | vcn_v2_5.c | 486 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
555 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
558 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1318 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_5_sriov_start()
|
| H A D | vcn_v3_0.c | 513 WREG32_SOC15(VCN, inst, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v3_0_mc_resume()
581 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
584 VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1403 mmUVD_VCPU_CACHE_SIZE0), in vcn_v3_0_start_sriov()
|
| H A D | vcn_v1_0.c | 368 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v1_0_mc_resume_spg_mode()
438 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
|