Home
last modified time | relevance | path

Searched refs:mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h706 #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX … macro
H A Dvcn_2_0_0_offset.h635 #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX … macro
H A Dvcn_3_0_0_offset.h1082 #define mmUVD_VCPU_CACHE_OFFSET5_BASE_IDX … macro