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Searched refs:mmUVD_STATUS (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c331 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
385 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
411 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
456 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
499 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
701 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
H A Duvd_v4_2.c215 if (RREG32(mmUVD_STATUS) != 0) in uvd_v4_2_hw_fini()
293 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v4_2_start()
347 status = RREG32(mmUVD_STATUS); in uvd_v4_2_start()
373 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v4_2_start()
418 status = RREG32(mmUVD_STATUS); in uvd_v4_2_stop()
461 WREG32(mmUVD_STATUS, 0); in uvd_v4_2_stop()
H A Duvd_v5_0.c213 if (RREG32(mmUVD_STATUS) != 0) in uvd_v5_0_hw_fini()
391 status = RREG32(mmUVD_STATUS); in uvd_v5_0_start()
417 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
479 WREG32(mmUVD_STATUS, 0); in uvd_v5_0_stop()
H A Dvcn_v1_0.c50 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
284 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
842 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
843 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
914 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v1_0_start_spg_mode()
948 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY; in vcn_v1_0_start_spg_mode()
949 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v1_0_start_spg_mode()
1165 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1200 WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0); in vcn_v1_0_stop_spg_mode()
1384 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
[all …]
H A Dvcn_v2_0.c58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
320 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
989 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start()
990 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
1064 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1095 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start()
1188 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1231 WREG32_SOC15(VCN, 0, mmUVD_STATUS, 0); in vcn_v2_0_stop()
1324 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1332 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
[all …]
H A Dvcn_v3_0.c65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
434 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
1162 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1163 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1237 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1269 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1375 mmUVD_STATUS), in vcn_v3_0_start_sriov()
1583 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
1628 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v3_0_stop()
2115 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
[all …]
H A Dvcn_v2_5.c61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
401 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
1033 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
1034 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
1117 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1152 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1287 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1442 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1480 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1786 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
[all …]
H A Duvd_v6_0.c537 if (RREG32(mmUVD_STATUS) != 0) in uvd_v6_0_hw_fini()
806 status = RREG32(mmUVD_STATUS); in uvd_v6_0_start()
833 WREG32_P(mmUVD_STATUS, 0, ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT)); in uvd_v6_0_start()
910 WREG32(mmUVD_STATUS, 0); in uvd_v6_0_stop()
1174 (RREG32(mmUVD_STATUS) & AMDGPU_UVD_STATUS_BUSY_MASK)) in uvd_v6_0_check_soft_reset()
H A Duvd_v7_0.c822 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
912 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
934 MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02); in uvd_v7_0_sriov_start()
1049 status = RREG32_SOC15(UVD, k, mmUVD_STATUS); in uvd_v7_0_start()
1079 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0, in uvd_v7_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h84 #define mmUVD_STATUS 0x3DAF macro
H A Duvd_4_2_d.h76 #define mmUVD_STATUS 0x3daf macro
H A Duvd_3_1_d.h78 #define mmUVD_STATUS 0x3daf macro
H A Duvd_5_0_d.h82 #define mmUVD_STATUS 0x3daf macro
H A Duvd_6_0_d.h98 #define mmUVD_STATUS 0x3daf macro
H A Duvd_7_0_offset.h208 #define mmUVD_STATUS … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h394 #define mmUVD_STATUS … macro
H A Dvcn_2_5_offset.h487 #define mmUVD_STATUS … macro
H A Dvcn_2_0_0_offset.h698 #define mmUVD_STATUS … macro
H A Dvcn_3_0_0_offset.h797 #define mmUVD_STATUS … macro