| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | uvd_v3_1.c | 341 WREG32_P(mmUVD_STATUS, 1<<2, ~(1<<2)); in uvd_v3_1_start()
395 status = RREG32(mmUVD_STATUS); in uvd_v3_1_start()
421 WREG32_P(mmUVD_STATUS, 0, ~(1<<2)); in uvd_v3_1_start()
466 status = RREG32(mmUVD_STATUS); in uvd_v3_1_stop()
509 WREG32(mmUVD_STATUS, 0); in uvd_v3_1_stop()
732 if (RREG32(mmUVD_STATUS) != 0) in uvd_v3_1_hw_fini()
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| H A D | vcn_v2_0.c | 59 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
328 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
996 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start_dpg_mode()
1019 tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_0_start()
1020 WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp); in vcn_v2_0_start()
1094 status = RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1125 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0, in vcn_v2_0_start()
1175 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_start()
1211 RREG32_SOC15(UVD, 0, mmUVD_STATUS); in vcn_v2_0_stop_dpg_mode()
1230 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
[all …]
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| H A D | vcn_v3_0.c | 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
456 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
1188 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); in vcn_v3_0_start_dpg_mode()
1215 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v3_0_start()
1216 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1290 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1322 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v3_0_start()
1380 RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v3_0_start()
1432 mmUVD_STATUS), in vcn_v3_0_start_sriov()
1627 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); in vcn_v3_0_stop_dpg_mode()
[all …]
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| H A D | vcn_v2_5.c | 62 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
521 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
1151 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); in vcn_v2_5_start_dpg_mode()
1180 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
1181 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
1255 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1290 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1341 RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1429 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1572 RREG32_SOC15(VCN, inst_idx, mmUVD_STATUS); in vcn_v2_5_stop_dpg_mode()
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 84 #define mmUVD_STATUS 0x3DAF macro
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| H A D | uvd_4_2_d.h | 76 #define mmUVD_STATUS 0x3daf macro
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| H A D | uvd_3_1_d.h | 78 #define mmUVD_STATUS 0x3daf macro
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| H A D | uvd_5_0_d.h | 82 #define mmUVD_STATUS 0x3daf macro
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| H A D | uvd_6_0_d.h | 98 #define mmUVD_STATUS 0x3daf macro
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| H A D | uvd_7_0_offset.h | 208 #define mmUVD_STATUS … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 394 #define mmUVD_STATUS … macro
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| H A D | vcn_2_5_offset.h | 487 #define mmUVD_STATUS … macro
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| H A D | vcn_2_0_0_offset.h | 698 #define mmUVD_STATUS … macro
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| H A D | vcn_3_0_0_offset.h | 797 #define mmUVD_STATUS … macro
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