Home
last modified time | relevance | path

Searched refs:mmUVD_SCRATCH2 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h46 #define mmUVD_SCRATCH2 … macro
H A Dvcn_2_5_offset.h419 #define mmUVD_SCRATCH2 … macro
H A Dvcn_2_0_0_offset.h404 #define mmUVD_SCRATCH2 … macro
H A Dvcn_3_0_0_offset.h695 #define mmUVD_SCRATCH2 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c982 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0); in vcn_v2_0_start_dpg_mode()
1348 RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF); in vcn_v2_0_pause_dpg_mode()
1461 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, in vcn_v2_0_dec_ring_set_wptr()
H A Dvcn_v3_0.c1168 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v3_0_start_dpg_mode()
1349 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); in vcn_v3_0_start()
1843 WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2, in vcn_v3_0_dec_ring_set_wptr()
H A Dvcn_v2_5.c1137 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()