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Searched refs:mmUVD_RB_WPTR4 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h226 #define mmUVD_RB_WPTR4 macro
H A Dvcn_2_5_offset.h589 #define mmUVD_RB_WPTR4 macro
H A Dvcn_2_0_0_offset.h940 #define mmUVD_RB_WPTR4 macro
H A Dvcn_3_0_0_offset.h919 #define mmUVD_RB_WPTR4 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c71 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
H A Dvcn_v2_0.c79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
H A Dvcn_v2_5.c82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
H A Dvcn_v3_0.c86 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),