| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_d.h | 43 #define mmUVD_RB_WPTR2 0x3c25 macro
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| H A D | uvd_7_0_offset.h | 92 #define mmUVD_RB_WPTR2 … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 214 #define mmUVD_RB_WPTR2 … macro
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| H A D | vcn_2_5_offset.h | 569 #define mmUVD_RB_WPTR2 … macro
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| H A D | vcn_2_0_0_offset.h | 926 #define mmUVD_RB_WPTR2 … macro
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| H A D | vcn_3_0_0_offset.h | 899 #define mmUVD_RB_WPTR2 … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v1_0.c | 67 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
994 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1220 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_stop_dpg_mode()
1299 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1653 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v1_0_enc_ring_get_wptr()
1671 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, in vcn_v1_0_enc_ring_set_wptr()
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| H A D | vcn_v2_0.c | 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
1136 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1159 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_stop_dpg_mode()
1294 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1621 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2); in vcn_v2_0_enc_ring_get_wptr()
1648 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
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| H A D | vcn_v2_5.c | 78 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
1194 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1412 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v2_5_stop_dpg_mode()
1551 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1690 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1717 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
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| H A D | vcn_v3_0.c | 82 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
1317 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1552 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v3_0_stop_dpg_mode()
1700 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
2014 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v3_0_enc_ring_get_wptr()
2041 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
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| H A D | uvd_v6_0.c | 128 return RREG32(mmUVD_RB_WPTR2); in uvd_v6_0_enc_ring_get_wptr()
160 WREG32(mmUVD_RB_WPTR2, in uvd_v6_0_enc_ring_set_wptr()
875 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
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| H A D | uvd_v7_0.c | 126 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2); in uvd_v7_0_enc_ring_get_wptr()
165 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, in uvd_v7_0_enc_ring_set_wptr()
1124 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
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