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Searched refs:mmUVD_RB_WPTR (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h48 #define mmUVD_RB_WPTR 0x3c2a macro
H A Duvd_7_0_offset.h102 #define mmUVD_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h224 #define mmUVD_RB_WPTR … macro
H A Dvcn_2_5_offset.h559 #define mmUVD_RB_WPTR … macro
H A Dvcn_2_0_0_offset.h936 #define mmUVD_RB_WPTR … macro
H A Dvcn_3_0_0_offset.h889 #define mmUVD_RB_WPTR … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
987 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1217 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_stop_dpg_mode()
1292 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1651 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v1_0_enc_ring_get_wptr()
1668 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, in vcn_v1_0_enc_ring_set_wptr()
H A Dvcn_v2_0.c73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
1127 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1156 tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v2_0_stop_dpg_mode()
1284 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1616 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR); in vcn_v2_0_enc_ring_get_wptr()
1641 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_enc_ring_set_wptr()
H A Dvcn_v2_5.c76 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
1185 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1409 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v2_5_stop_dpg_mode()
1541 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1685 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v2_5_enc_ring_get_wptr()
1710 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
H A Dvcn_v3_0.c80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
1308 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1549 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v3_0_stop_dpg_mode()
1690 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
2009 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v3_0_enc_ring_get_wptr()
2034 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_enc_ring_set_wptr()
H A Duvd_v6_0.c126 return RREG32(mmUVD_RB_WPTR); in uvd_v6_0_enc_ring_get_wptr()
157 WREG32(mmUVD_RB_WPTR, in uvd_v6_0_enc_ring_set_wptr()
868 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
H A Duvd_v7_0.c124 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR); in uvd_v7_0_enc_ring_get_wptr()
162 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, in uvd_v7_0_enc_ring_set_wptr()
1117 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()