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Searched refs:mmUVD_RB_SIZE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h46 #define mmUVD_RB_SIZE 0x3c28 macro
H A Duvd_7_0_offset.h98 #define mmUVD_RB_SIZE … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h220 #define mmUVD_RB_SIZE … macro
H A Dvcn_2_5_offset.h555 #define mmUVD_RB_SIZE … macro
H A Dvcn_2_0_0_offset.h932 #define mmUVD_RB_SIZE … macro
H A Dvcn_3_0_0_offset.h885 #define mmUVD_RB_SIZE … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
1130 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_start()
1282 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_0_pause_dpg_mode()
2001 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c83 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
1188 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1363 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), in vcn_v2_5_sriov_start()
1539 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v3_0.c87 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
1311 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_start()
1448 mmUVD_RB_SIZE), in vcn_v3_0_start_sriov()
1688 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v3_0_pause_dpg_mode()
H A Dvcn_v1_0.c72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
990 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_start_spg_mode()
1290 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v1_0_pause_dpg_mode()
H A Duvd_v7_0.c925 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4); in uvd_v7_0_sriov_start()
1120 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4); in uvd_v7_0_start()
H A Duvd_v6_0.c871 WREG32(mmUVD_RB_SIZE, ring->ring_size / 4); in uvd_v6_0_start()