| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_6_0_d.h | 42 #define mmUVD_RB_RPTR2 0x3c24 macro
|
| H A D | uvd_7_0_offset.h | 90 #define mmUVD_RB_RPTR2 … macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 212 #define mmUVD_RB_RPTR2 … macro
|
| H A D | vcn_2_5_offset.h | 567 #define mmUVD_RB_RPTR2 … macro
|
| H A D | vcn_2_0_0_offset.h | 924 #define mmUVD_RB_RPTR2 … macro
|
| H A D | vcn_3_0_0_offset.h | 897 #define mmUVD_RB_RPTR2 … macro
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v1_0.c | 66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
993 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
1221 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1298 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode()
1636 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v1_0_enc_ring_get_rptr()
|
| H A D | vcn_v2_0.c | 74 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
1135 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_start()
1160 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1293 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode()
1598 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2); in vcn_v2_0_enc_ring_get_rptr()
|
| H A D | vcn_v2_5.c | 77 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
1193 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1413 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1550 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1667 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
|
| H A D | vcn_v3_0.c | 81 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
1316 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_start()
1553 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1699 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode()
1991 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v3_0_enc_ring_get_rptr()
|
| H A D | uvd_v6_0.c | 98 return RREG32(mmUVD_RB_RPTR2); in uvd_v6_0_enc_ring_get_rptr()
874 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
|
| H A D | uvd_v7_0.c | 92 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2); in uvd_v7_0_enc_ring_get_rptr()
1123 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
|