/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_6_0_d.h | 47 #define mmUVD_RB_RPTR 0x3c29 macro
|
H A D | uvd_7_0_offset.h | 100 #define mmUVD_RB_RPTR … macro
|
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
H A D | vcn_1_0_offset.h | 222 #define mmUVD_RB_RPTR … macro
|
H A D | vcn_2_5_offset.h | 557 #define mmUVD_RB_RPTR … macro
|
H A D | vcn_2_0_0_offset.h | 934 #define mmUVD_RB_RPTR … macro
|
H A D | vcn_3_0_0_offset.h | 887 #define mmUVD_RB_RPTR … macro
|
/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | vcn_v1_0.c | 64 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 986 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode() 1218 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode() 1291 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_pause_dpg_mode() 1634 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v1_0_enc_ring_get_rptr()
|
H A D | vcn_v2_0.c | 72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 1126 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_start() 1157 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode() 1283 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_0_pause_dpg_mode() 1596 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR); in vcn_v2_0_enc_ring_get_rptr()
|
H A D | vcn_v2_5.c | 75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 1184 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start() 1410 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode() 1540 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode() 1665 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
|
H A D | vcn_v3_0.c | 79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), 1307 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_start() 1550 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode() 1689 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v3_0_pause_dpg_mode() 1989 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v3_0_enc_ring_get_rptr()
|
H A D | uvd_v6_0.c | 96 return RREG32(mmUVD_RB_RPTR); in uvd_v6_0_enc_ring_get_rptr() 867 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
|
H A D | uvd_v7_0.c | 90 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR); in uvd_v7_0_enc_ring_get_rptr() 1116 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_start()
|