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Searched refs:mmUVD_RB_BASE_LO4 (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h412 #define mmUVD_RB_BASE_LO4 … macro
H A Dvcn_2_5_offset.h581 #define mmUVD_RB_BASE_LO4 … macro
H A Dvcn_2_0_0_offset.h762 #define mmUVD_RB_BASE_LO4 … macro
H A Dvcn_3_0_0_offset.h911 #define mmUVD_RB_BASE_LO4 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c72 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
H A Dvcn_v3_0.c79 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
H A Dvcn_v2_5.c75 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),