Home
last modified time | relevance | path

Searched refs:mmUVD_RB_BASE_LO (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h44 #define mmUVD_RB_BASE_LO 0x3c26 macro
H A Duvd_7_0_offset.h94 #define mmUVD_RB_BASE_LO … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h216 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_2_5_offset.h551 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_2_0_0_offset.h928 #define mmUVD_RB_BASE_LO … macro
H A Dvcn_3_0_0_offset.h881 #define mmUVD_RB_BASE_LO … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c66 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1158 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1329 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
2056 SOC15_REG_OFFSET(UVD, 0, mmUVD_RB_BASE_LO), in vcn_v2_0_start_sriov()
H A Dvcn_v3_0.c73 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1362 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1499 mmUVD_RB_BASE_LO), in vcn_v3_0_start_sriov()
1756 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
H A Dvcn_v2_5.c69 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
1324 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1499 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1692 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()