| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v2_0.c | 58 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
801 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_disable_static_power_gating()
807 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_disable_static_power_gating()
820 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS); in vcn_v2_0_enable_static_power_gating()
823 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data); in vcn_v2_0_enable_static_power_gating()
864 tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS); in vcn_v2_0_start_dpg_mode()
867 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp); in vcn_v2_0_start_dpg_mode()
961 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
990 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), in vcn_v2_0_start_dpg_mode()
1188 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
[all …]
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| H A D | vcn_v3_0.c | 65 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
715 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_disable_static_power_gating()
721 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_disable_static_power_gating()
732 data = RREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS); in vcn_v3_0_enable_static_power_gating()
735 WREG32_SOC15(VCN, inst, mmUVD_POWER_STATUS, data); in vcn_v3_0_enable_static_power_gating()
1038 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v3_0_start_dpg_mode()
1041 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v3_0_start_dpg_mode()
1044 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v3_0_start_dpg_mode()
1147 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
1182 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v3_0_start_dpg_mode()
[all …]
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| H A D | vcn_v2_5.c | 60 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
61 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
1009 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
1012 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
1015 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
1116 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1145 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
1176 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
1549 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1562 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
[all …]
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| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 65 #define mmUVD_POWER_STATUS 0x38FC macro
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| H A D | uvd_4_2_d.h | 91 #define mmUVD_POWER_STATUS 0x38fc macro
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| H A D | uvd_3_1_d.h | 93 #define mmUVD_POWER_STATUS 0x38fc macro
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| H A D | uvd_5_0_d.h | 103 #define mmUVD_POWER_STATUS 0x38c4 macro
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| H A D | uvd_6_0_d.h | 119 #define mmUVD_POWER_STATUS 0x38c4 macro
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| H A D | uvd_7_0_offset.h | 28 #define mmUVD_POWER_STATUS … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 32 #define mmUVD_POWER_STATUS … macro
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| H A D | vcn_2_5_offset.h | 399 #define mmUVD_POWER_STATUS … macro
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| H A D | vcn_2_0_0_offset.h | 384 #define mmUVD_POWER_STATUS … macro
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| H A D | vcn_3_0_0_offset.h | 667 #define mmUVD_POWER_STATUS … macro
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