Searched refs:mmUVD_MPC_SET_MUX (Results 1 – 19 of 19) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
| H A D | uvd_4_0_d.h | 55 #define mmUVD_MPC_SET_MUX 0x3D7D macro
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| H A D | uvd_4_2_d.h | 58 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_3_1_d.h | 60 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_5_0_d.h | 64 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_6_0_d.h | 80 #define mmUVD_MPC_SET_MUX 0x3d7d macro
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| H A D | uvd_7_0_offset.h | 174 #define mmUVD_MPC_SET_MUX … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 354 #define mmUVD_MPC_SET_MUX … macro
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| H A D | vcn_2_5_offset.h | 769 #define mmUVD_MPC_SET_MUX … macro
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| H A D | vcn_2_0_0_offset.h | 604 #define mmUVD_MPC_SET_MUX … macro
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| H A D | vcn_3_0_0_offset.h | 1149 #define mmUVD_MPC_SET_MUX … macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | uvd_v3_1.c | 366 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v3_1_start()
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| H A D | uvd_v4_2.c | 326 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v4_2_start()
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| H A D | uvd_v5_0.c | 372 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v5_0_start()
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| H A D | vcn_v1_0.c | 883 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v1_0_start_spg_mode()
1066 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v1_0_start_dpg_mode()
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| H A D | vcn_v2_0.c | 899 UVD, 0, mmUVD_MPC_SET_MUX), in vcn_v2_0_start_dpg_mode()
1032 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v2_0_start()
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| H A D | vcn_v2_5.c | 928 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
1084 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v2_5_start()
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| H A D | vcn_v3_0.c | 1048 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1214 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v3_0_start()
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| H A D | uvd_v6_0.c | 786 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v6_0_start()
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| H A D | uvd_v7_0.c | 1026 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); in uvd_v7_0_start()
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