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Searched refs:mmUVD_MASTINT_EN (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h52 #define mmUVD_MASTINT_EN 0x3D40 macro
H A Duvd_4_2_d.h47 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_3_1_d.h47 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_5_0_d.h53 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_6_0_d.h69 #define mmUVD_MASTINT_EN 0x3d40 macro
H A Duvd_7_0_offset.h152 #define mmUVD_MASTINT_EN macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v3_1.c354 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v3_1_start()
419 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v3_1_start()
H A Dvcn_v2_0.c884 UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_0_start_dpg_mode()
940 UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start_dpg_mode()
1030 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0, in vcn_v2_0_start()
1120 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), in vcn_v2_0_start()
H A Dvcn_v3_0.c1061 VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v3_0_start_dpg_mode()
1121 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1226 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v3_0_start()
1317 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v3_0_start()
H A Dvcn_v2_5.c1032 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
1094 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
1194 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1285 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h330 #define mmUVD_MASTINT_EN macro
H A Dvcn_2_5_offset.h533 #define mmUVD_MASTINT_EN macro
H A Dvcn_2_0_0_offset.h538 #define mmUVD_MASTINT_EN macro
H A Dvcn_3_0_0_offset.h863 #define mmUVD_MASTINT_EN macro