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Searched refs:mmUVD_LMI_RBC_IB_VMID (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_d.h74 #define mmUVD_LMI_RBC_IB_VMID 0x3da1 macro
H A Duvd_6_0_d.h90 #define mmUVD_LMI_RBC_IB_VMID 0x3da1 macro
H A Duvd_7_0_offset.h194 #define mmUVD_LMI_RBC_IB_VMID macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h380 #define mmUVD_LMI_RBC_IB_VMID macro
H A Dvcn_2_5_offset.h971 #define mmUVD_LMI_RBC_IB_VMID macro
H A Dvcn_2_0_0_offset.h674 #define mmUVD_LMI_RBC_IB_VMID macro
H A Dvcn_3_0_0_offset.h1487 #define mmUVD_LMI_RBC_IB_VMID macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c1030 amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0)); in uvd_v6_0_ring_emit_ib()
H A Duvd_v7_0.c1329 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0)); in uvd_v7_0_ring_emit_ib()
H A Dvcn_v1_0.c1557 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0)); in vcn_v1_0_dec_ring_emit_ib()