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Searched refs:mmUVD_JRBC_RB_REF_DATA (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v1_0.c88 reg = SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA); in jpeg_v1_0_decode_ring_set_patch_ring()
101 …ring->ring[ptr++] = PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0… in jpeg_v1_0_decode_ring_set_patch_ring()
259 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_fence()
345 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_ib()
365 PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_JRBC_RB_REF_DATA), 0, 0, PACKETJ_TYPE0)); in jpeg_v1_0_decode_ring_emit_reg_wait()
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h278 #define mmUVD_JRBC_RB_REF_DATA … macro
H A Dvcn_2_5_offset.h145 #define mmUVD_JRBC_RB_REF_DATA … macro
H A Dvcn_2_0_0_offset.h130 #define mmUVD_JRBC_RB_REF_DATA … macro
H A Dvcn_3_0_0_offset.h343 #define mmUVD_JRBC_RB_REF_DATA … macro