Home
last modified time | relevance | path

Searched refs:mmUVD_GP_SCRATCH4 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h45 #define mmUVD_GP_SCRATCH4 0x3D38 macro
H A Duvd_6_0_d.h132 #define mmUVD_GP_SCRATCH4 0x3d38 macro
H A Duvd_7_0_offset.h148 #define mmUVD_GP_SCRATCH4 … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h318 #define mmUVD_GP_SCRATCH4 … macro
H A Dvcn_2_5_offset.h641 #define mmUVD_GP_SCRATCH4 … macro
H A Dvcn_2_0_0_offset.h526 #define mmUVD_GP_SCRATCH4 … macro
H A Dvcn_3_0_0_offset.h991 #define mmUVD_GP_SCRATCH4 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v7_0.c726 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v7_0_mc_resume()
862 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); in uvd_v7_0_sriov_start()
H A Duvd_v6_0.c635 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v6_0_mc_resume()