Searched refs:mmUVD_DPG_LMA_MASK (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_vcn.h | 82 ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
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| H A D | vcn_v1_0.c | 80 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
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| H A D | vcn_v2_0.c | 88 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
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| H A D | vcn_v2_5.c | 91 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
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| H A D | vcn_v3_0.c | 95 SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK),
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| /linux/drivers/gpu/drm/amd/include/asic_reg/vcn/ |
| H A D | vcn_1_0_offset.h | 40 #define mmUVD_DPG_LMA_MASK … macro
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| H A D | vcn_2_5_offset.h | 413 #define mmUVD_DPG_LMA_MASK … macro
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| H A D | vcn_2_0_0_offset.h | 398 #define mmUVD_DPG_LMA_MASK … macro
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| H A D | vcn_3_0_0_offset.h | 689 #define mmUVD_DPG_LMA_MASK … macro
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