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Searched refs:mmUVD_CGC_GATE (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h35 #define mmUVD_CGC_GATE 0x3D2A macro
H A Duvd_4_2_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_3_1_d.h42 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_5_0_d.h48 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_6_0_d.h64 #define mmUVD_CGC_GATE 0x3d2a macro
H A Duvd_7_0_offset.h144 #define mmUVD_CGC_GATE … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h304 #define mmUVD_CGC_GATE … macro
H A Dvcn_2_5_offset.h497 #define mmUVD_CGC_GATE … macro
H A Dvcn_2_0_0_offset.h504 #define mmUVD_CGC_GATE … macro
H A Dvcn_3_0_0_offset.h813 #define mmUVD_CGC_GATE … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v3_0.c794 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_GATE); in vcn_v3_0_disable_clock_gating()
816 WREG32_SOC15(VCN, inst, mmUVD_CGC_GATE, data); in vcn_v3_0_disable_clock_gating()
818 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
948 VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c768 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
790 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
792 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
898 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
H A Duvd_v3_1.c344 WREG32(mmUVD_CGC_GATE, 0); in uvd_v3_1_start()
H A Dvcn_v2_0.c561 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
582 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
687 UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()