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Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c683 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
722 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
777 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
780 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
786 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
789 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
854 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
H A Duvd_v3_1.c213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
229 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
605 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
608 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
614 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
H A Duvd_v4_2.c618 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
621 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
627 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
630 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
641 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
657 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
H A Duvd_v6_0.c1340 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1380 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1437 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1440 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1446 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1449 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1519 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
H A Dvcn_v1_0.c513 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
521 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
546 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
567 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
637 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
644 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
646 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
667 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
725 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_0.c540 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
547 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
572 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
593 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
670 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
700 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
707 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
709 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
730 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
H A Dvcn_v2_5.c627 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
634 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
662 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
683 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
761 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
792 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
799 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
801 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
821 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
H A Dvcn_v3_0.c746 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
753 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
781 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
802 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
902 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
930 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
937 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
939 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
960 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
H A Duvd_v7_0.c866 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
979 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
H A Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
H A Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
H A Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
H A Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro