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Searched refs:mmTCP_CHAN_STEER_LO (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c261 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876,
H A Dgfx_v9_0.c692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
H A Dgfx_v6_0.c1614 chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull); in gfx_v6_0_setup_tcc()
1636 WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer)); in gfx_v6_0_setup_tcc()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2104 #define mmTCP_CHAN_STEER_LO 0x2b03 macro
H A Dgfx_7_2_d.h2125 #define mmTCP_CHAN_STEER_LO 0x2b03 macro
H A Dgfx_8_1_d.h2296 #define mmTCP_CHAN_STEER_LO 0x2b03 macro
H A Dgfx_8_0_d.h2317 #define mmTCP_CHAN_STEER_LO 0x2b03 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h1710 #define mmTCP_CHAN_STEER_LO … macro
H A Dgc_9_1_offset.h1999 #define mmTCP_CHAN_STEER_LO … macro
H A Dgc_9_2_1_offset.h1941 #define mmTCP_CHAN_STEER_LO … macro