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Searched refs:mmSQ_UTCL1_STATUS (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h427 #define mmSQ_UTCL1_STATUS … macro
H A Dgc_9_1_offset.h421 #define mmSQ_UTCL1_STATUS … macro
H A Dgc_9_2_1_offset.h417 #define mmSQ_UTCL1_STATUS … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c205 SOC15_REG_ENTRY_STR(GC, 0, mmSQ_UTCL1_STATUS),