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Searched refs:mmSQ_EDC_CNT (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h168 #define mmSQ_EDC_CNT … macro
H A Dgc_9_0_offset.h569 #define mmSQ_EDC_CNT … macro
H A Dgc_9_1_offset.h563 #define mmSQ_EDC_CNT … macro
H A Dgc_10_1_0_offset.h2553 #define mmSQ_EDC_CNT … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c4585 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT), 0, 4, 16}, in gfx_v9_0_do_edc_gds_workarounds()
6551 { "SQ_LDS_D", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6555 { "SQ_LDS_I", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6559 { "SQ_SGPR", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6563 { "SQ_VGPR0", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6567 { "SQ_VGPR1", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6571 { "SQ_VGPR2", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),
6575 { "SQ_VGPR3", SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_CNT),