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Searched refs:mmSQC_ICACHE_UTCL1_STATUS (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h661 #define mmSQC_ICACHE_UTCL1_STATUS … macro
H A Dgc_9_1_offset.h655 #define mmSQC_ICACHE_UTCL1_STATUS … macro
H A Dgc_9_2_1_offset.h633 #define mmSQC_ICACHE_UTCL1_STATUS … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c204 SOC15_REG_ENTRY_STR(GC, 0, mmSQC_ICACHE_UTCL1_STATUS),