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Searched refs:mmSDMA0_UTCL1_WR_XNACK0 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h150 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
H A Dsdma0_4_0_offset.h152 #define mmSDMA0_UTCL1_WR_XNACK0 0x0045 macro
H A Dsdma0_4_2_2_offset.h152 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
H A Dsdma0_4_2_offset.h152 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c75 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
H A Dsdma_v5_0.c74 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
H A Dsdma_v4_0.c87 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_UTCL1_WR_XNACK0),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h127 #define mmSDMA0_UTCL1_WR_XNACK0 … macro
H A Dgc_10_3_0_offset.h126 #define mmSDMA0_UTCL1_WR_XNACK0 … macro