Searched refs:mmSDMA0_STATUS_REG (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_2.c | 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
1426 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); in sdma_v5_2_is_idle()
1442 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1443 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1444 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1445 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
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| H A D | sdma_v5_0.c | 63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
1510 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); in sdma_v5_0_is_idle()
1526 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v5_0_wait_for_idle()
1527 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); in sdma_v5_0_wait_for_idle()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 86 #define mmSDMA0_STATUS_REG … macro
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| H A D | sdma0_4_0_offset.h | 88 #define mmSDMA0_STATUS_REG 0x0025 macro
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| H A D | sdma0_4_2_2_offset.h | 88 #define mmSDMA0_STATUS_REG … macro
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| H A D | sdma0_4_2_offset.h | 88 #define mmSDMA0_STATUS_REG … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 169 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_3_0_1_d.h | 166 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_2_0_d.h | 232 #define mmSDMA0_STATUS_REG 0x340d macro
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| H A D | oss_3_0_d.h | 303 #define mmSDMA0_STATUS_REG 0x340d macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 63 #define mmSDMA0_STATUS_REG … macro
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