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Searched refs:mmSDMA0_STATUS_REG (Results 1 – 17 of 17) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
1444 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); in sdma_v5_2_is_idle()
1460 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1461 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1462 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
1463 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG)); in sdma_v5_2_wait_for_idle()
H A Dsdma_v5_0.c63 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
1539 u32 tmp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS_REG)); in sdma_v5_0_is_idle()
1555 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); in sdma_v5_0_wait_for_idle()
1556 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG)); in sdma_v5_0_wait_for_idle()
H A Dcik.c1052 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
1053 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
H A Dsdma_v4_0.c76 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS_REG),
2024 u32 tmp = RREG32_SDMA(i, mmSDMA0_STATUS_REG); in sdma_v4_0_is_idle()
2041 sdma[j] = RREG32_SDMA(j, mmSDMA0_STATUS_REG); in sdma_v4_0_wait_for_idle()
H A Dvi.c676 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET},
677 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET},
H A Dnv.c342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
H A Dsoc15.c390 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h86 #define mmSDMA0_STATUS_REG … macro
H A Dsdma0_4_0_offset.h88 #define mmSDMA0_STATUS_REG 0x0025 macro
H A Dsdma0_4_2_2_offset.h88 #define mmSDMA0_STATUS_REG … macro
H A Dsdma0_4_2_offset.h88 #define mmSDMA0_STATUS_REG … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h169 #define mmSDMA0_STATUS_REG 0x340d macro
H A Doss_3_0_1_d.h166 #define mmSDMA0_STATUS_REG 0x340d macro
H A Doss_2_0_d.h232 #define mmSDMA0_STATUS_REG 0x340d macro
H A Doss_3_0_d.h303 #define mmSDMA0_STATUS_REG 0x340d macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h63 #define mmSDMA0_STATUS_REG … macro
H A Dgc_10_3_0_offset.h70 #define mmSDMA0_STATUS_REG … macro