Searched refs:mmSDMA0_STATUS1_REG (Results 1 – 13 of 13) sorted by relevance
| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 88 #define mmSDMA0_STATUS1_REG … macro
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| H A D | sdma0_4_0_offset.h | 90 #define mmSDMA0_STATUS1_REG 0x0026 macro
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| H A D | sdma0_4_2_2_offset.h | 90 #define mmSDMA0_STATUS1_REG … macro
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| H A D | sdma0_4_2_offset.h | 90 #define mmSDMA0_STATUS1_REG … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 170 #define mmSDMA0_STATUS1_REG 0x340e macro
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| H A D | oss_3_0_1_d.h | 167 #define mmSDMA0_STATUS1_REG 0x340e macro
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| H A D | oss_2_0_d.h | 233 #define mmSDMA0_STATUS1_REG 0x340e macro
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| H A D | oss_3_0_d.h | 304 #define mmSDMA0_STATUS1_REG 0x340e macro
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_2.c | 65 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
1517 stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); in sdma_v5_2_reset_queue()
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| H A D | sdma_v5_0.c | 64 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
1616 stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); in sdma_v5_0_reset_queue()
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| H A D | sdma_v4_0.c | 77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_STATUS1_REG),
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 65 #define mmSDMA0_STATUS1_REG … macro
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| H A D | gc_10_3_0_offset.h | 72 #define mmSDMA0_STATUS1_REG … macro
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