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Searched refs:mmSDMA0_RLC3_RB_WPTR_POLL_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
H A Dsdma_v4_0.c220 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_2_2_offset.h644 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL … macro
H A Dsdma0_4_2_offset.h640 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h633 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL … macro
H A Dgc_10_3_0_offset.h646 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL … macro