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Searched refs:mmSDMA0_RLC0_RB_WPTR_POLL_CNTL (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h304 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … macro
H A Dsdma0_4_0_offset.h392 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x0147 macro
H A Dsdma0_4_2_2_offset.h392 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … macro
H A Dsdma0_4_2_offset.h388 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h219 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 macro
H A Doss_3_0_1_d.h258 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 macro
H A Doss_2_0_d.h273 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 macro
H A Doss_3_0_d.h380 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL 0x3505 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
191 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
199 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
214 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff0, 0x00403000),
336 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
H A Dsdma_v5_0.c120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h384 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … macro
H A Dgc_10_3_0_offset.h382 #define mmSDMA0_RLC0_RB_WPTR_POLL_CNTL … macro