Searched refs:mmSDMA0_RLC0_RB_WPTR (Results 1 – 19 of 19) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_amdkfd_arcturus.c | 165 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_arcturus_hqd_sdma_load()
170 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_arcturus_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v7.c | 272 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
274 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v8.c | 295 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); in kgd_hqd_sdma_load()
297 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v10_3.c | 401 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in hqd_sdma_load_v10_3()
406 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in hqd_sdma_load_v10_3()
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| H A D | amdgpu_amdkfd_gfx_v10.c | 415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 426 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
431 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, in kgd_hqd_sdma_load()
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| H A D | sdma_v5_2.c | 101 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
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| H A D | sdma_v5_0.c | 100 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
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| H A D | sdma_v4_0.c | 113 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_WPTR),
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 300 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | sdma0_4_0_offset.h | 388 #define mmSDMA0_RLC0_RB_WPTR 0x0145 macro
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| H A D | sdma0_4_2_2_offset.h | 388 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | sdma0_4_2_offset.h | 384 #define mmSDMA0_RLC0_RB_WPTR … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 218 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_3_0_1_d.h | 257 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_2_0_d.h | 272 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| H A D | oss_3_0_d.h | 379 #define mmSDMA0_RLC0_RB_WPTR 0x3504 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 380 #define mmSDMA0_RLC0_RB_WPTR … macro
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| H A D | gc_10_3_0_offset.h | 378 #define mmSDMA0_RLC0_RB_WPTR … macro
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