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Searched refs:mmSDMA0_RLC0_RB_RPTR (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c158 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_arcturus_hqd_sdma_load()
274 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_arcturus_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v7.c268 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
491 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v8.c291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
526 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v10_3.c394 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in hqd_sdma_load_v10_3()
582 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in hqd_sdma_destroy_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
658 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
H A Damdgpu_amdkfd_gfx_v9.c419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
608 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
H A Dsdma_v5_2.c99 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
H A Dsdma_v5_0.c98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
H A Dsdma_v4_0.c111 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_RB_RPTR),
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h296 #define mmSDMA0_RLC0_RB_RPTR macro
H A Dsdma0_4_0_offset.h384 #define mmSDMA0_RLC0_RB_RPTR 0x0143 macro
H A Dsdma0_4_2_2_offset.h384 #define mmSDMA0_RLC0_RB_RPTR macro
H A Dsdma0_4_2_offset.h380 #define mmSDMA0_RLC0_RB_RPTR macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h217 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
H A Doss_3_0_1_d.h256 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
H A Doss_2_0_d.h271 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
H A Doss_3_0_d.h378 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h376 #define mmSDMA0_RLC0_RB_RPTR macro
H A Dgc_10_3_0_offset.h374 #define mmSDMA0_RLC0_RB_RPTR macro