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Searched refs:mmSDMA0_RLC0_IB_BASE_LO (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h316 #define mmSDMA0_RLC0_IB_BASE_LO … macro
H A Dsdma0_4_0_offset.h404 #define mmSDMA0_RLC0_IB_BASE_LO 0x014d macro
H A Dsdma0_4_2_2_offset.h404 #define mmSDMA0_RLC0_IB_BASE_LO … macro
H A Dsdma0_4_2_offset.h400 #define mmSDMA0_RLC0_IB_BASE_LO … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h227 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d macro
H A Doss_3_0_1_d.h266 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d macro
H A Doss_2_0_d.h281 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d macro
H A Doss_3_0_d.h388 #define mmSDMA0_RLC0_IB_BASE_LO 0x350d macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c103 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
H A Dsdma_v5_2.c104 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_RLC0_IB_BASE_LO),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h396 #define mmSDMA0_RLC0_IB_BASE_LO … macro