| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | cik_sdma.c | 901 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
904 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
906 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
909 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
911 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
914 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
916 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
919 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
|
| H A D | sdma_v4_0.c | 143 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
189 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051),
335 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051),
1277 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1280 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
1289 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); in sdma_v4_1_init_power_gating()
1296 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); in sdma_v4_1_init_power_gating()
2284 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
2287 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); in sdma_v4_0_update_medium_grain_light_sleep()
2292 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); in sdma_v4_0_update_medium_grain_light_sleep()
[all …]
|
| H A D | sdma_v3_0.c | 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
1471 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1475 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1479 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1483 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_light_sleep()
1531 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]); in sdma_v3_0_get_clockgating_state()
|
| H A D | sdma_v5_2.c | 1799 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_2_update_medium_grain_light_sleep()
1802 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_2_update_medium_grain_light_sleep()
1806 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_2_update_medium_grain_light_sleep()
1809 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_2_update_medium_grain_light_sleep()
1864 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_2_get_clockgating_state()
|
| H A D | sdma_v5_0.c | 1840 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_0_update_medium_grain_light_sleep()
1843 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_0_update_medium_grain_light_sleep()
1847 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); in sdma_v5_0_update_medium_grain_light_sleep()
1850 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); in sdma_v5_0_update_medium_grain_light_sleep()
1900 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL)); in sdma_v5_0_get_clockgating_state()
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 64 #define mmSDMA0_POWER_CNTL … macro
|
| H A D | sdma0_4_0_offset.h | 66 #define mmSDMA0_POWER_CNTL 0x001a macro
|
| H A D | sdma0_4_2_2_offset.h | 66 #define mmSDMA0_POWER_CNTL … macro
|
| H A D | sdma0_4_2_offset.h | 66 #define mmSDMA0_POWER_CNTL … macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 159 #define mmSDMA0_POWER_CNTL 0x3402 macro
|
| H A D | oss_3_0_1_d.h | 156 #define mmSDMA0_POWER_CNTL 0x3402 macro
|
| H A D | oss_2_0_d.h | 221 #define mmSDMA0_POWER_CNTL 0x3402 macro
|
| H A D | oss_3_0_d.h | 293 #define mmSDMA0_POWER_CNTL 0x3402 macro
|
| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 41 #define mmSDMA0_POWER_CNTL … macro
|
| H A D | gc_10_3_0_offset.h | 48 #define mmSDMA0_POWER_CNTL … macro
|