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Searched refs:mmSDMA0_PHASE1_QUANTUM (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h102 #define mmSDMA0_PHASE1_QUANTUM … macro
H A Dsdma0_4_0_offset.h104 #define mmSDMA0_PHASE1_QUANTUM 0x002d macro
H A Dsdma0_4_2_2_offset.h104 #define mmSDMA0_PHASE1_QUANTUM … macro
H A Dsdma0_4_2_offset.h104 #define mmSDMA0_PHASE1_QUANTUM … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h177 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
H A Doss_3_0_1_d.h175 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
H A Doss_2_0_d.h240 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
H A Doss_3_0_d.h312 #define mmSDMA0_PHASE1_QUANTUM 0x3415 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_0.c1015 WREG32_SDMA(i, mmSDMA0_PHASE1_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h79 #define mmSDMA0_PHASE1_QUANTUM … macro