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Searched refs:mmSDMA0_GFX_RB_RPTR_HI (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h212 #define mmSDMA0_GFX_RB_RPTR_HI … macro
H A Dsdma0_4_0_offset.h216 #define mmSDMA0_GFX_RB_RPTR_HI 0x0084 macro
H A Dsdma0_4_2_2_offset.h216 #define mmSDMA0_GFX_RB_RPTR_HI … macro
H A Dsdma0_4_2_offset.h212 #define mmSDMA0_GFX_RB_RPTR_HI … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c79 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
565 …WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring-… in sdma_v5_2_gfx_resume_instance()
570 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_2_gfx_resume_instance()
H A Dsdma_v5_0.c78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
747 …WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring-… in sdma_v5_0_gfx_resume_instance()
752 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); in sdma_v5_0_gfx_resume_instance()
H A Dsdma_v4_0.c91 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR_HI),
1103 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR_HI, 0); in sdma_v4_0_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h210 #define mmSDMA0_GFX_RB_RPTR_HI … macro
H A Dgc_10_3_0_offset.h198 #define mmSDMA0_GFX_RB_RPTR_HI … macro