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Searched refs:mmSDMA0_GFX_RB_RPTR (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h210 #define mmSDMA0_GFX_RB_RPTR … macro
H A Dsdma0_4_0_offset.h214 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
H A Dsdma0_4_2_2_offset.h214 #define mmSDMA0_GFX_RB_RPTR … macro
H A Dsdma0_4_2_offset.h210 #define mmSDMA0_GFX_RB_RPTR … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h190 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_3_0_1_d.h217 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_2_0_d.h249 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_3_0_d.h342 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_2.c78 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
564 …WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wp… in sdma_v5_2_gfx_resume_instance()
569 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_2_gfx_resume_instance()
H A Dsdma_v5_0.c77 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
746 …WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wp… in sdma_v5_0_gfx_resume_instance()
751 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); in sdma_v5_0_gfx_resume_instance()
H A Dsdma_v2_4.c438 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
H A Dsdma_v4_0.c90 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_RB_RPTR),
1102 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0); in sdma_v4_0_gfx_resume()
H A Dcik_sdma.c464 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
H A Dsdma_v3_0.c679 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h208 #define mmSDMA0_GFX_RB_RPTR … macro
H A Dgc_10_3_0_offset.h196 #define mmSDMA0_GFX_RB_RPTR … macro