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Searched refs:mmSDMA0_GFX_IB_RPTR (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h226 #define mmSDMA0_GFX_IB_RPTR macro
H A Dsdma0_4_0_offset.h230 #define mmSDMA0_GFX_IB_RPTR 0x008b macro
H A Dsdma0_4_2_2_offset.h230 #define mmSDMA0_GFX_IB_RPTR macro
H A Dsdma0_4_2_offset.h226 #define mmSDMA0_GFX_IB_RPTR macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h198 #define mmSDMA0_GFX_IB_RPTR 0x348b macro
H A Doss_3_0_1_d.h225 #define mmSDMA0_GFX_IB_RPTR 0x348b macro
H A Doss_2_0_d.h257 #define mmSDMA0_GFX_IB_RPTR 0x348b macro
H A Doss_3_0_d.h350 #define mmSDMA0_GFX_IB_RPTR 0x348b macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v2_4.c440 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
H A Dcik_sdma.c466 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
H A Dsdma_v3_0.c681 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
H A Dsdma_v5_2.c86 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
H A Dsdma_v5_0.c85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
H A Dsdma_v4_0.c98 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_RPTR),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h224 #define mmSDMA0_GFX_IB_RPTR macro
H A Dgc_10_3_0_offset.h212 #define mmSDMA0_GFX_IB_RPTR macro