| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v3_0.c | 84 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
103 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
122 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
136 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
150 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
170 mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
523 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_stop()
525 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_stop()
731 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v3_0_gfx_resume()
737 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v3_0_gfx_resume()
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| H A D | sdma_v5_2.c | 85 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
422 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_stop()
424 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_stop()
670 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_gfx_resume_instance()
676 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_gfx_resume_instance()
873 mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_mqd_init()
1494 ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_2_reset_queue()
1496 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_2_reset_queue()
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| H A D | mxgpu_vi.c | 108 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
247 mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
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| H A D | sdma_v5_0.c | 84 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
603 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_stop()
605 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_stop()
854 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_gfx_resume_instance()
860 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_gfx_resume_instance()
1016 mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_mqd_init()
1594 ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); in sdma_v5_0_reset_queue()
1596 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); in sdma_v5_0_reset_queue()
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| H A D | sdma_v2_4.c | 347 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_stop()
349 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_stop()
461 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]); in sdma_v2_4_gfx_resume()
467 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in sdma_v2_4_gfx_resume()
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| H A D | sdma_v4_0.c | 97 SOC15_REG_ENTRY_STR(GC, 0, mmSDMA0_GFX_IB_CNTL),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
187 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100),
931 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); in sdma_v4_0_gfx_enable()
933 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); in sdma_v4_0_gfx_enable()
1156 ib_cntl = RREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL); in sdma_v4_0_gfx_resume()
1162 WREG32_SDMA(i, mmSDMA0_GFX_IB_CNTL, ib_cntl); in sdma_v4_0_gfx_resume()
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| H A D | cik_sdma.c | 318 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
492 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl); in cik_sdma_gfx_resume()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 224 #define mmSDMA0_GFX_IB_CNTL … macro
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| H A D | sdma0_4_0_offset.h | 228 #define mmSDMA0_GFX_IB_CNTL 0x008a macro
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| H A D | sdma0_4_2_2_offset.h | 228 #define mmSDMA0_GFX_IB_CNTL … macro
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| H A D | sdma0_4_2_offset.h | 224 #define mmSDMA0_GFX_IB_CNTL … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 197 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_3_0_1_d.h | 224 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_2_0_d.h | 256 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| H A D | oss_3_0_d.h | 349 #define mmSDMA0_GFX_IB_CNTL 0x348a macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 222 #define mmSDMA0_GFX_IB_CNTL … macro
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| H A D | gc_10_3_0_offset.h | 210 #define mmSDMA0_GFX_IB_CNTL … macro
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