| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v2_4.c | 384 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
389 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
951 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
953 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
958 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in sdma_v2_4_soft_reset()
960 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in sdma_v2_4_soft_reset()
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| H A D | cik_sdma.c | 410 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in cik_sdma_enable()
415 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl); in cik_sdma_enable()
1064 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_soft_reset()
1066 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
1070 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); in cik_sdma_soft_reset()
1072 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_sdma_soft_reset()
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| H A D | sdma_v5_2.c | 517 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable()
519 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable()
661 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_gfx_resume_instance()
663 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_2_gfx_resume_instance()
1525 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_reset_queue()
1527 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_reset_queue()
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| H A D | sdma_v5_0.c | 701 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable()
703 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable()
845 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_gfx_resume_instance()
847 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_0_gfx_resume_instance()
1624 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_reset_queue()
1626 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_reset_queue()
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| H A D | sdma_v4_0.c | 1057 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_enable()
1059 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); in sdma_v4_0_enable()
1420 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL); in sdma_v4_0_start()
1422 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp); in sdma_v4_0_start()
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| H A D | sdma_v3_0.c | 621 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v3_0_enable()
626 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_enable()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 96 #define mmSDMA0_F32_CNTL … macro
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| H A D | sdma0_4_0_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
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| H A D | sdma0_4_2_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| H A D | sdma0_4_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 174 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_3_0_1_d.h | 172 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_2_0_d.h | 237 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_3_0_d.h | 309 #define mmSDMA0_F32_CNTL 0x3412 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 73 #define mmSDMA0_F32_CNTL … macro
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| H A D | gc_10_3_0_offset.h | 80 #define mmSDMA0_F32_CNTL … macro
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