Searched refs:mmSDMA0_F32_CNTL (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 671 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_enable() 673 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_enable() 815 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_gfx_resume_instance() 817 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_0_gfx_resume_instance() 1603 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_0_stop_queue() 1605 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_0_stop_queue()
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| H A D | sdma_v5_2.c | 518 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_enable() 520 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_enable() 662 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_gfx_resume_instance() 664 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); in sdma_v5_2_gfx_resume_instance() 1515 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); in sdma_v5_2_stop_queue() 1517 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); in sdma_v5_2_stop_queue()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 96 #define mmSDMA0_F32_CNTL … macro
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| H A D | sdma0_4_0_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
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| H A D | sdma0_4_2_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| H A D | sdma0_4_2_offset.h | 98 #define mmSDMA0_F32_CNTL … macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 174 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_3_0_1_d.h | 172 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_2_0_d.h | 237 #define mmSDMA0_F32_CNTL 0x3412 macro
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| H A D | oss_3_0_d.h | 309 #define mmSDMA0_F32_CNTL 0x3412 macro
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_1_0_offset.h | 73 #define mmSDMA0_F32_CNTL … macro
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