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Searched refs:mmSDMA0_CNTL (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v5_0.c629 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_ctx_switch_enable()
643 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_0_ctx_switch_enable()
793 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_gfx_resume_instance()
798 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v5_0_gfx_resume_instance()
1599 cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_0_stop_queue()
1601 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); in sdma_v5_0_stop_queue()
1682 sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) : in sdma_v5_0_set_trap_irq_state()
1683 sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_CNTL); in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v5_2.c488 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_ctx_switch_enable()
491 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); in sdma_v5_2_ctx_switch_enable()
640 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_gfx_resume_instance()
645 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); in sdma_v5_2_gfx_resume_instance()
1508 cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); in sdma_v5_2_stop_queue()
1510 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); in sdma_v5_2_stop_queue()
1588 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL); in sdma_v5_2_set_trap_irq_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h68 #define mmSDMA0_CNTL … macro
H A Dsdma0_4_0_offset.h70 #define mmSDMA0_CNTL 0x001c macro
H A Dsdma0_4_2_2_offset.h70 #define mmSDMA0_CNTL … macro
H A Dsdma0_4_2_offset.h70 #define mmSDMA0_CNTL … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h161 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_3_0_1_d.h158 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_2_0_d.h223 #define mmSDMA0_CNTL 0x3404 macro
H A Doss_3_0_d.h295 #define mmSDMA0_CNTL 0x3404 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h45 #define mmSDMA0_CNTL … macro