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Searched refs:mmSCRATCH_REG0 (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h213 #define mmSCRATCH_REG0 … macro
H A Dgc_9_0_offset.h4641 #define mmSCRATCH_REG0 … macro
H A Dgc_9_1_offset.h4871 #define mmSCRATCH_REG0 … macro
H A Dgc_9_2_1_offset.h4827 #define mmSCRATCH_REG0 … macro
H A Dgc_10_1_0_offset.h7125 #define mmSCRATCH_REG0 … macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c1861 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ring()
1868 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); in gfx_v6_0_ring_test_ring()
1873 tmp = RREG32(mmSCRATCH_REG0); in gfx_v6_0_ring_test_ring()
1968 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ib()
1975 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; in gfx_v6_0_ring_test_ib()
1990 tmp = RREG32(mmSCRATCH_REG0); in gfx_v6_0_ring_test_ib()
H A Dgfx_v9_0.c1197 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_ring_test_ring()
1826 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h404 #define mmSCRATCH_REG0 0xc040 macro
H A Dgfx_7_2_d.h416 #define mmSCRATCH_REG0 0xc040 macro
H A Dgfx_8_1_d.h454 #define mmSCRATCH_REG0 0xc040 macro
H A Dgfx_8_0_d.h454 #define mmSCRATCH_REG0 0xc040 macro